Design and Implementation of UTMI using Asynchronous QCA Technology

Authors:D. VASANTHI, K. RAJENDRA PRASAD

1457-1460

VLSI Design for PRPG Circuit in Built In Self Test for Compression

Authors:M. AMRUTHA, S. T. MRUDULA

1461-1465

Low-Power Hybrid Trace-Back Register Exchange Method of SMU for Viterbi Decoder

Authors:V.SUSHMA, G.VIJAYA

1466-1473

High Performance ALU Design Implementation using Modified Wallace MAC with Realization of Multi-Operand Adders

Authors:K.KANAKA KUMARI, B.SANDEEP KUMAR

1474-1477

An Implementation of Multicore Analysis using Altera DE2

Authors:K. ASHOKKUMAR, DR. P. GOWRISANKAR

1478-1481

A Dynamic Clock Gating Technique to Reduce Power Consumption in ALU Design

Authors:A.NARESH KUMAR, T.SWARNA LATHA

1482-1486

Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile Wimax Systems

Authors:GELAYE GERESU, LAMESSA DINGETA

1487-1491

Optimization of Delay by using Reversible Logic Compressor Based Vedic Multiplier

Authors:J.NARENDRA, CHANDRA SHEKAR

1492-1497

Reconfigurable Architecture of Adaptive Median Filter- an FPGA Based Approach for Impulse Noise Suppression

Authors:G. GANESH, G. SAMATHA

1498-1500

Design and Analysis of Sub-Threshold Adiabatic Logic for Low Power Applications

Authors:D. USEN

1501-1504